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RM0008
General-purpose timer (TIMx)
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 121. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
Write TIF=0
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 122 gives an overview of the external trigger input block.
Figure 122. External trigger input block
or
TI2F
TI1F
TRGI
or
or
encoder
mode
external clock
mode 1
CK_PSC
ETR pin
ETR
0
1
divider
/1, /2, /4, /8
ETRP
CK_INT
filter
downcounter
ETRF
CK_INT
(internal clock)
external clock
mode 2
internal clock
mode
ETP
ETPS[1:0]
ETF[3:0]
TIMx_SMCR
TIMx_SMCR
TIMx_SMCR
ECE
SMS[2:0]
TIMx_SMCR
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
2.
3.
4.
5.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Doc ID 13902 Rev 9
333/995
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